From silicon to organic nanoparticle memory devices

D. Tsoukalas

Abstract

After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

1. Introduction

Memories represent by far the largest part of electronic systems, and there is a strong driving force to develop novel structures. The purpose is to find materials and concepts that will lead to devices that are scalable for at least several generations below 50 nm, non-volatile and fast (nanosecond range; Clementi & Bez 2005). The technology and materials must also be compatible with present and future generations of complementary metal oxide semiconductors. This is quite an ambitious goal, with phase change memories being probably the most challenging approach.

In parallel, there is an upsurge of interest in plastic electronics, that is, transistors and other devices based on polymeric or low molecular weight organic semiconductors. Such low-cost devices will not compete directly with single-crystal silicon in terms of operation speed, but are likely to form components of display drivers in portable computers and pagers and the basis of transaction cards and identification tags. It is interesting to see how mainstream technology has fostered research on plastic memory devices during recent years. A good example of this is the case of nanoparticle memories.

The purpose of this review is to present the developments from silicon-based nanoparticle memories to hybrid silicon and organic material devices and finally to organic-based nanoparticle memories. The term ‘nanoparticle memories’ is used, throughout this review, to mean the flash-type memory structure. Resistive memories that might use nanoparticles within an organic material matrix will not be discussed here.

2. Silicon-based nanoparticle memories

Electronic non-volatile memory technology is actually based on flash memories (Fazio 2004). A flash memory cell is fabricated using silicon technology and its principle of operation is closely related to the operation of a metal oxide field effect transistor (MOSFET). In a flash cell, a continuous layer of poly-silicon film is buried within the insulator of the MOSFET, separated by a thin insulator, called tunnelling oxide, from the channel area of the transistor and by a thicker insulator, named control oxide, from the gate.

The device operates through the application of voltage pulses to the gate, allowing electrons from the silicon channel to cross the tunnelling oxide barrier and charge the floating gate. Thus, the electrostatic potential of the floating gate screens the electrons of the channel, and the current between source and drain is substantially reduced. To remove the electrons from the floating gate, an opposite polarity voltage pulse is applied, which brings them back to the silicon channel. In this case, we observe that the source–drain current increases again. These two states represent the write and erase states of the device. The reading operation is performed at a gate voltage that will not disturb the writing and erasing states of the device.

Research in scaling flash memory technology is underway using the approach described above or using different approaches based on local storage of the electrons. One important advantage of local storage is the possibility of further scaling the thickness of the tunnelling oxide, as any defect present in that oxide would allow only local loss of stored information, which is not the case for a continuous storage medium, where any defect between the floating gate and the channel of the transistor will result in complete loss of the charge. A nitride layer can replace poly-silicon for local storage (Eitan et al. 2000). Nanoparticles have been introduced for charge storage by Tiwari et al. (1996) as another method of local storage of the charge (figure 1).

Figure 1.

Schematic of a nanoparticle memory device.

To achieve that goal nanoparticles should be electrically isolated from each other. Silicon and germanium have initially been widely used as nanoparticle materials because of their compatibility with silicon technology. The formation of a two-dimensional layer of nanoparticles is a critical step in the realization of a nanoparticle memory device. For that purpose, two major techniques have been widely investigated: ion-beam synthesis of nanoparticles (Kapetanakis et al. 2000) and chemical vapour deposition (Muralidhar et al. 2003). Ion-beam synthesis is performed by implanting silicon at very low implantation energy within a thin silicon oxide layer, followed by annealing at a high temperature. Both approaches have resulted in the demonstration of high-performance devices (Dimitrakis et al. 2004; Gerardi et al. 2007).

Metallic nanoparticles have been less well explored as charge storage elements in nanocrystal memory devices. In principle, metal nanoparticles should present advantages over silicon nanocrystal memories. The higher electron affinity of several metals compared with silicon allows the potential well of the storage nodes to be engineered to create an asymmetric barrier between the silicon channel and the storage nodes (figure 2).

Figure 2.

Energy barriers in the particular case of a metallic nanoparticle with higher work function than silicon (channel area).

This form of barrier makes the write operation easier by creating a higher energy barrier to movement in the other direction by electrons, which favours retention characteristics. During the erase operation, the nanocrystal Fermi level is brought above the silicon conduction band edge, enabling a high erase current to pass through the tunnelling oxide. On the other hand, the high density of states around the Fermi level in a metallic nanoparticle reduces the influence of traps at the nanoparticle/oxide interface, which seems not to be the case for silicon nanocrystals. Quantum confinement determines the conditions for charge retention in the silicon nanocrystals since strongly confined nanocrystal electron states lie at higher energies than the conduction band edge in the silicon substrate and should ease out tunnelling. If, however, experimental data show good retention of silicon nanocrystal memories, this rather suggests that the injected charges fall into interface traps of nanocrystals with the oxide matrix.

Research on metallic nanoparticles for floating gate memories is more limited and more recent than corresponding research efforts on semiconductor nanoparticles. Investigations are based on the deposition of thin metallic films on top of a tunnelling thermal oxide using evaporation (Liu et al. 2002; Lee, C. H. et al. 2005; Lee, J. J. et al. 2005; Dufourcq et al. 2008). Deposition is followed by rapid thermal annealing (RTA) at 800°C, resulting in the formation of metallic nanoparticles whose size and density distribution depends on RTA conditions and the thickness of the deposited thin film. The resulting floating gate memory devices prepared using this technique show clear memory windows without any contamination of the silicon substrate, which was monitored by carrier lifetime measurements. This technique will be further explored with future generations of metallic gate MOS devices since it allows more flexibility in nanoparticle energy barrier engineering. A more versatile technique for room temperature deposition of metallic nanoparticles under high vacuum has also been presented recently (Verrelli et al. 2007).

Realizations of memories that are based on the nanoparticle concept discussed above but combining hybrid structures (silicon with organic materials) or purely organic materials have appeared more recently in the literature and will be covered in the next sections of this review. Research on these devices is of an exploratory nature and the purpose is not to replace silicon-based memories but rather to find new areas of application. One important issue for these devices is the possibility of fabricating them at low temperatures, which opens up possibilities for their integration in three-dimensional architecture.

3. Realization of hybrid silicon organic nanoparticle memories

Besides the vacuum technique mentioned above for the low temperature deposition of nanoparticles, in recent years we have also investigated methods using chemical self-assembly. Along these lines, a silicon FET was used in a similar way to flash memory device architecture in order to probe the charge storage properties of gold nanoparticles.

The device structure is shown in figure 3 and the silicon device fabrication process has been described in detail elsewhere (Kolliopoulou et al. 2003). The memory stack is made up of a 5 nm thermal SiO2 bottom, numbered (3), a gold nanoparticle layer in the middle (2) and a 54 nm organic insulator on top (1).

Figure 3.

Schematic of a device realized on a silicon on insulator wafer. S and D are the source and drain of the device and C is the channel area. The memory stack is made of a 5 nm SiO2 bottom (3), a gold nanoparticle layer in the middle (2) and an organic insulator on top (1).

The gold nanoparticles were deposited on the SiO2 substrates at room temperature by two methods. The first method was the Langmuir–Blodgett (LB) technique using a Molecular Photonics LB700 trough. The subphase was purified water obtained from a reverse osmosis/deionization/UV sterilization system; the film depositions were undertaken at a subphase pH of 5.8±0.2 and a temperature of 20±2°C. These nanoparticles were of a nominal diameter of 10 nm and were passivated with tri-n-octylphosphine oxide/octadecylamine, which makes the nanoparticles soluble in various organic liquids but mainly insoluble in water; the Q-Au is thus suitable for LB deposition. More processing details can be found in Paul et al. (2003) where a hysteresis in MOS capacitors has been also observed using the above film within the insulator stack.

The second method used for gold nanoparticle layer deposition on the SiO2 substrate was chemical processing by self-assembly. Using this process, the SiO2 surface was first functionalized with an amine by placing the wafers into a 10 per cent silane solution (1 ml 3-aminopropyltriethoxysilane in 9 ml toluene) for 1 h in a nitrogen environment. They were then washed in toluene and sonicated in a fresh toluene solution and dichloromethane solution for 2 min each. This process was repeated twice. The chemical reaction that takes place at the oxide surface covers the SiO2 layer with an amine compound, leaving a –NH2 functionality exposed. The functionalized substrate was dried with nitrogen and held under running ultra-pure water for 1–2 min to encourage charging of the amino groups prior to exposure to the nanoparticles. This surface was then dipped into a solution of carboxylic acid (–COOH) derivatized gold nanoparticles. The gold nanoparticles were passivated with organic ligands (Kolliopoulou et al. 2003). Provided that the pH was adjusted correctly, the acid and amine were mutually attracted. The nanoparticles were therefore positioned at a distance from the SiO2 surface equal to the length of the amine plus the acid ‘units’, probably 5–6 nm.

Cadmium arachidate (CdA) film was used to cap the layer with gold nanoparticles. Twenty CdA layers, corresponding to a total thickness of 54 nm, were deposited by the LB technique using a Molecular Photonics LB700 trough. CdA films were obtained by spreading arachidic acid (Sigma, 99% purity) on a water subphase containing 2.5×10−4 M cadmium chloride (BDH, Analar grade). The deposition pressure for these fatty acid salt films was 22 mN m−1.

Tests and measurements of the memory characteristics of these devices consist of the successive application of positive or negative voltage pulses on the gate of a previously unstressed device, keeping source and drain electrodes grounded. The voltage pulse height progressively increases while the pre-selected pulse duration is kept constant. The injected (rejected) charges into (out of) the gold nanoparticles cause a shift of the transistor threshold voltage to higher or lower values compared with the unstressed device. The high Vth state is usually called the write state and the low Vth state is called the erase state.

The final device exhibits a clear memory window under different gate bias pulses of 1 s duration, as shown in figures 4 and 5. The devices in both cases present non-volatile characteristics (Kolliopoulou et al. 2003).

Figure 4.

The effect of the programming voltage on the memory window for a pulse of 1 s using chemical self-assembly as the gold deposition technique. VDS=100 mV, W/L=10 μm/1.5 μm, pulse duration = 1 s. Open diamond, erase; filled diamond, write.

Figure 5.

Write/erase memory window after application of gate voltage pulses with 1 s duration using LB deposition of gold. VDS=100 mV, W/L=10 μm/1.5 μm, pulse duration = 1 s. Open diamond, erase; filled diamond, write.

For this pulse duration, the charge exchange takes place between the nanocrystals and the metal gate electrode, leading to counterclockwise hysteresis. The hysteresis direction indicates that electrons are extracted from the nanoparticles for positive gate voltages and injected into them from the gate electrode for negative gate voltages. Although the thermal SiO2 layer used is relatively thin (5 nm), for self-assembly deposited nanoparticles the distance between the surface of the silicon and the gold particles is effectively increased to over 10 nm because of the presence of the amine capping layer plus the acid units associated with the gold nanoparticles and for LB-deposited nanoparticles is increased to 7 nm, with 2 nm corresponding to the length of the organic ligand. In the latter case, the application of pulses with a shorter time duration, 300 ms, reveals the effect of nanoparticle charge exchange with the channel (figure 6).

Figure 6.

The device memory window for a pulse duration of 300 ms (gold nanoparticles were deposited by LB). IDS(Vh)=50 nA.

This charge exchange takes place when the gate voltage does not exceed a value of 5 V. At this voltage the leakage from the organic insulator that separates the nanoparticles from the gate is low but time dependent. After 300 ms, the current density increases, compensating for charges from the channel area. At pulse voltages higher than 5 V, the current density is high enough even for durations of 300 ms or less, so the nanoparticles start to interact with the gate from the very beginning of the pulse application. This enhanced conduction masks the effect of channel charge exchange. The organic insulator breaks down at voltage values higher than those shown in figures 4 and 5, and therefore no plateau can be reached within the measurement range. We have investigated the insulating properties of CdA in more detail in a previous work (Kolliopoulou et al. 2003). We observed that the current flowing through 20 monolayers of CdA is higher than the current through a 5 nm SiO2 layer. According to Nabok et al. (2002) the conduction mechanism of LB insulating films is due to (i) direct tunnelling through each LB bilayer and (ii) thermally activated hopping within the plane of carboxylic head groups. Table 1 summarizes the electron affinities (χ) and the work functions (Φ) of these materials. Comparison of the electron barrier heights φ leads to the conclusion that transport through the CdA is much easier than through the SiO2 insulating layer for the same equivalent thickness.

View this table:
Table 1.

Electronic properties of metals and insulators used.

The replacement of the organic material used above as the control insulator by a less leaky one is a challenge for that type of device. Promising new results (Halik et al. 2004) show the way ahead for high-quality organic insulating materials. Inorganic insulators deposited at low temperature with reduced fixed charge could also be investigated as control oxides. Recently poly(methyl methacrylate) as well as pentacene have been evaluated as organic insulators quite successfully (Mabrook et al. 2008).

The planar device fabrication process presented above has also been extended to a three-dimensional architecture that exhibits similar non-volatile memory behaviour with planar devices (Kolliopoulou et al. 2006). This scenario involves the combination of new processes such as wafer bonding at low temperatures, anisotropic etching of silicon for the realization of source–drain areas together with chemical self-assembly and LB deposition of CdA as the organic insulator. The device channel is made of SiGe and the complete process does not exceed the 400°C deposition temperature limit of low temperature oxide (LTO) that plays the role of tunnelling oxide. The complete structure is shown in figure 7. It is also interesting to remark that in order to realize the three-dimensional memory devices it was also necessary to successfully overcome the problem of LB deposition of a CdA organic insulator over non-planar structures.

Figure 7.

The schematic of a three-dimensional memory device. Layer SOG stands for spin on glass, a material that is used to bond the two wafers (substrate and active), and LTO is used as the tunnelling insulator. (1), LB insulator; (2), gold nanoparticles; (3), LTO; (4), n+ Si.

4. Realization of organic nanoparticle memories

More recently, efforts to demonstrate flash-type memory devices that also replace the channel with an organic semiconductor have seen the light of publicity. Below, this research is briefly reviewed, and it is expected that in the coming years other interesting new results will appear in this direction. It appears that there is plenty of room for the investigation of new organic materials not only for use as the semiconductive channel but also for the tunnelling and control insulators. It is important also to report that memory organic FET devices with ferroelectric insulators have been fabricated by Schroeder et al. (2004), but this is not the focus of the current paper.

The first attempt to demonstrate a nanoparticle-based memory organic FET device was performed by Liu et al. (2006). Their device, which uses poly(3-hexylthiophene) as the channel material, also uses an organic material (poly(4-vinylphenol)) for the tunnelling barrier but the control oxide is still thermal SiO2. Another innovation of this fabrication process is the ink-jet printing of metal contacts for the source and drain. The device and its fabrication process sequence are shown in figure 8.

Figure 8.

Processing sequence and final three-terminal nanoparticle organic memory (PEI, polyethyleneimine; PSS, polystyrenesulphonate; PAH, poly(allylamine hydrochloride); PVP, poly(4-vinylphenol); PEDOT, poly(3,4-ethylenedioxythiophene); P3HT, poly(3-hexylthiophene); S, source; D, drain). Adapted from Liu et al. (2006).

The effect of the gold nanoparticle layer on the memory performance of the device was clearly demonstrated, although trapping was also partially attributed to the organic insulators used and their interfaces. The on/off ratio of the current is 1500, which degrades after 100 cycles in ambient.

Memory organic FETs using pentacene deposited in a vacuum as the active semiconductive channel over a layer of gold nanoparticles previously self-assembled on a thick SiO2 layer have also been demonstrated by Novembre et al. (2008). These devices operate at very high voltages owing to the large thickness of the insulator. The effect of nanoparticle contribution to the high current on/off ratio observed after applying opposite polarity voltage pulses to the gate (silicon substrate) was clear. A similar approach has previously been presented by Leong et al. (2007) using two-terminal devices with a smaller SiO2 oxide thickness (4.5 nm) that allows gate control at much smaller voltages. The device structure is shown in figure 9.

Figure 9.

Two-terminal organic device (APTES, aminopropyltriethoxysilane). Adapted from Leong et al. (2007).

The charging of nanoparticles takes place from holes injected from the gold electrode through the influence of the gate (silicon substrate). In both these research works, it appears that charge is trapped in the nanoparticle, although there is no insulator that separates the nanoparticles from the channel (except from the ligand molecules). It is expected that the retention of such devices will be limited. More recently, two-terminal devices using gold nanoparticles synthesized within a block copolymer (polystyrene-block-poly(4-vinylpyridine)) over a pentacene layer demonstrated charge storage following charge exchange between the nanoparticles and pentacene (Leong et al. 2008). In that case, the block copolymer acts as the insulating material and retention is good.

5. Conclusions

The research carried out to extend the well-established concept of silicon nanocrystal memories to corresponding devices using organic materials has been reviewed in this work. Studies during the last 5 years have gradually evolved from hybrid structures that use a silicon channel to organic channel nanoparticle memory devices. The work performed has demonstrated the possibility of injecting charge into the nanoparticles that can control the current between source and drain in organic material channels. When also combined with new technologies such as ink-jet printing, organic materials can probably provide submicrometre non-volatile memory devices processed at room temperature. On the other hand, using advanced lithographic techniques such as e-beam, nanometre-scale organic transistors have been demonstrated (Collet et al. 2000) and there is no reason why memory devices at such dimensions cannot be demonstrated as well in the future. There are many interesting processes that can result in organic nanoparticle memory devices operating at low voltage and built on plastic substrates.

Acknowledgements

The author would like to thank all his collaborators who have contributed to the realization of silicon memories or hybrid silicon organic devices; M. C. Petty, S. Paul, P. Normand, S. Kolliopoulou, and P. Dimitrakis are particularly acknowledged.

Footnotes

References

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